How computers and chips work

The first principle

Every computation, from adding two numbers to answering a question in a chatbot, reduces to switching: a voltage is either high or low, and that pair of states can stand for 1 and 0, true and false. A transistor is a switch that one electrical signal turns on or off with no moving parts, so a chip that packs billions of them can perform billions of logical steps every second. The whole history of computing follows from making that switch smaller, because a smaller transistor switches faster, uses less energy and lets more of them share one chip, and the whole geopolitics of chips follows from how hard and costly that shrinking has become.

The core

From a switch to a processor

• The transistor. A metal oxide semiconductor field effect transistor (MOSFET), the type in almost every chip, has a source and a drain separated by silicon that normally does not conduct. A voltage on a third terminal, the gate, which sits on a thin insulating layer, pulls charge carriers into a thin channel under it, and current flows; remove the voltage and it stops. Why doped silicon behaves this way is explained in the note on new materials and semiconductors.
• Logic gates. A few transistors wired together make a gate such as AND, OR or NOT, whose output follows a fixed rule from its inputs. Gates combine into adders that do arithmetic and into memory cells that hold a bit, and since any calculation can be broken into such steps, a large enough collection of gates can compute anything a program describes.
• The processor. A central processing unit (CPU) fetches an instruction from memory, decodes it, executes it and stores the result, ticking through this cycle billions of times a second to the beat of a clock. The instruction set is the vocabulary a processor understands; x86 and Arm are licensed, while RISC-V is an open instruction set that anyone may use without paying for it.
• Different chips for different work. A CPU does a few complex tasks very fast one after another, a graphics processing unit (GPU) does thousands of simple calculations side by side, which is why training artificial intelligence needs thousands of GPUs, and memory chips such as dynamic random access memory (DRAM) and NAND flash store data rather than process it.

Moore's law and the node

• Moore's law is Gordon Moore's observation of 1965, revised in 1975, that the number of transistors on a chip doubles about every two years. It is an industry trend, not a law of nature, and it has slowed as transistors approach a few dozen atoms across, where current leaks through barriers and heat is hard to remove.
• The node is a label. Names such as 7, 5 or 3 nanometre once measured a transistor feature but are now marketing labels for a generation of technology; each new node packs transistors more densely, and each costs more to build. Chips at older nodes, 28 nanometre and above, still run cars, appliances and power systems, and they are where new entrants usually start.

How a chip is made

• Wafers. Sand is refined into polysilicon of extreme purity, melted and pulled as a single crystal ingot, and sliced into polished wafers, today 300 millimetres across.
• Design. Engineers describe the circuit in software using electronic design automation tools, a market dominated by a few American firms, and verify it before a single wafer is touched.
• Fabrication. In a fabrication plant, or fab, the design is printed onto the wafer layer by layer by photolithography: a light sensitive coating is exposed through a patterned mask, developed, and the exposed areas are etched, doped or coated. The finest features need extreme ultraviolet (EUV) light of 13.5 nanometre wavelength, and the machines that produce it come from one company, ASML of the Netherlands.
• Assembly, testing, marking and packaging (ATMP). The finished wafer is cut into dies, and each die is tested, connected to the outside and sealed in a package. Firms that do this for others are called outsourced semiconductor assembly and test (OSAT) firms, and advanced packaging, which stacks or joins several dies, is now as important as shrinking transistors.

Dimensions

• Economic. Chips sit in everything from phones to power grids, so their supply decides the cost and timing of almost every manufactured good, as the shortage of 2020 to 2022 showed when car plants worldwide stopped for want of cheap chips.
• Strategic. The chain has chokepoints held by a few countries: EUV machines in the Netherlands, design software in the United States, leading edge fabrication in Taiwan and South Korea. Since October 2022 the United States has restricted exports of advanced chips and chip making tools to China, which has made chips a tool of foreign policy, and the United States CHIPS and Science Act of 2022 and similar laws elsewhere pay fabs to locate at home, so India competes in a subsidy race.
• Industrial models. An integrated device manufacturer designs and makes its own chips (Intel, Samsung), a fabless company only designs (Qualcomm, Nvidia), a foundry only makes chips for others (TSMC), and an OSAT firm packages them; India's strength is design, since a large share of the world's chip design engineers work in India, mostly for global fabless firms.
• Environmental and human. A fab uses large volumes of ultrapure water, much electricity and fluorinated gases with high warming potential, so siting and water security matter, and it needs thousands of trained technicians whom it takes as long to train as the plant takes to build.

In practice

• India Semiconductor Mission (ISM). Approved in December 2021 with Rs 76,000 crore under the Ministry of Electronics and Information Technology (MeitY), it offered to pay half the project cost of fabs, display fabs, compound semiconductor plants and ATMP units, alongside the Design Linked Incentive scheme for chip design firms. About a dozen projects were approved under it, the largest being the Tata Electronics fab at Dholera in Gujarat with Powerchip Semiconductor Manufacturing Corporation of Taiwan, approved in February 2024.
• First production. Micron's assembly and test plant for memory chips at Sanand in Gujarat, approved in June 2023, began commercial production in early 2026, and other packaging units approved at Sanand, Jagiroad in Assam and Jewar in Uttar Pradesh are at various stages.
• Semicon 2.0. On 15 July 2026 the Union Cabinet approved a second phase with Rs 1.27 lakh crore across six pillars: design, machines and materials, fabs, packaging, research and development, and talent. Support is now graded, with 40 per cent of capital cost for silicon wafer fabs, 35 per cent for compound semiconductor and display fabs and advanced packaging, and 25 per cent for older packaging, so that the subsidy falls as the risk falls.
• Indigenous designs and computing. The Shakti processors from the Indian Institute of Technology Madras and the Digital India RISC-V programme build on the open instruction set, the government's Semi-Conductor Laboratory (SCL) at Mohali makes older node chips for strategic use, and the National Supercomputing Mission of 2015, run by the Department of Science and Technology and MeitY through the Centre for Development of Advanced Computing (C-DAC), builds India's supercomputers.

Issues and way forward

• Ecosystem, not plants. A fab depends on hundreds of suppliers of gases, chemicals, equipment and spare parts that India does not yet have, so Semicon 2.0's support for machines and materials is as important as support for the fab itself.
• Yield and time. A new fab takes years to build and then months or years before most of its chips work, so policy must be stable across governments and patient about returns.
• Talent. The design workforce is large but fabrication skills are thin, so training through institutes and industry, and bringing back experienced Indian engineers from abroad, has to begin before plants open.
• Products of our own. Indian design engineers mostly work on foreign products, so India needs its own fabless firms and its own product companies; demand from government buyers, defence and telecom can give them a first market.

Common confusions

• Fab and ATMP. A fab builds transistors into a wafer and is the costly, hard step, while an ATMP or OSAT unit cuts, tests and packages finished wafers, which is cheaper and quicker to set up.
• Foundry and fabless. A foundry manufactures chips designed by others, while a fabless firm designs chips and pays a foundry to make them.
• Node and feature size. A 3 nanometre node does not mean any part of the transistor measures 3 nanometres; it names a generation.
• CPU and GPU. A CPU does a few complex tasks in sequence, while a GPU does thousands of simple tasks in parallel.
• Instruction set and chip. An instruction set such as RISC-V is a specification of what a chip understands, while a chip is a physical design that implements it.

For the exam

• Keyword bank: transistor as a switch, logic gate, Moore's law, process node, wafer, photolithography, extreme ultraviolet lithography, fab, foundry and fabless, ATMP and OSAT, advanced packaging, chokepoint, RISC-V, India Semiconductor Mission, Semicon 2.0.
• Previous year questions: Practise the previous year questions on this topic →
• Use in an answer:
  • Introduction with data: In July 2026 the Union Cabinet approved Semicon 2.0 with Rs 1.27 lakh crore, after the first India Semiconductor Mission of Rs 76,000 crore drew about a dozen chip and packaging projects.
  • Introduction with a source: Gordon Moore observed in 1965 that the number of components on a chip doubles at a steady rate, and that trend, now slowing, has driven sixty years of cheaper computing.
  • Conclusion: India has entered the chip chain at its two easier ends, design and packaging; the test of the mission is whether a working fab and its suppliers follow without a fresh subsidy for each plant.
  • Conclusion: A chip is a concentration of physics, chemistry and supply chains, so self reliance in chips will come from building an ecosystem and a workforce, not from a single factory.